No 5:Title: Design Verification Engineer
Responsibility:
· Contributes to project verification plan development for SOC end to
end testing following IP integration.
· Contributes to verification testbench design and implementation for
Verilog and System Verilog solutions.
· Expands upon a coverage driven constrained random test suite
development methodology.
Extensive test development, debug and coverage analysis to identify
all design defects.
Heavily involved or leading functional and gate simulation efforts
using Cadence and Synopsys tools.
· May perform other duties in areas of digital design, synthesis and
timing analysis as individual skills enable contributions in these
areas.
Requirement:
· 1. Bachelor, Master or above in Electronic, Communications,
Microelectronics Engineering and Computer Science.
· 2. experience in digital design based on high-level
languages(preferable Verilog and/or C),with knowledge of IC design
flow, including coding, simulation, verification, synthesis, DFT
and STA.
· 3. Must be able to communicate in both written and spoken English;
· 4. good communication skills and the ability to work well as a
team;
· 5. knowledge in Verilog, testbench architecture, verification flow;
· 6. knowledge of formal verification is a bonus
· 7. Familiar with mainstream EDA tools from Synopsis, Cadence and
Mentor, like NC-Verilog, VCS, DC/PC, RC, PrimeTime, Fastscan and so
on.
· 8. Languages: Verilog, C/C++, System Verilog, Perl/TCL, UNIX
scripting.
都是人才啊
